1. Field of the Invention
The present invention relates to a method for fabricating a flash memory device, and more particularly, to a method for fabricating a NOR flash memory device.
2. Description of the Related Art
Among various semiconductor memory devices, a random access memory (RAM) loses data when power is interrupted. A read only memory (ROM), however, retains data even when power is interrupted. Thus, such a ROM is called a non-volatile memory device. A flash memory device is a non-volatile memory device which allows information to be electrically erased or recorded (programmed), and is widely used in computers and memory cards. The flash memory device can be either a NOR flash memory device or a NAND flash memory device. Here, a conventional NOR flash memory device will be described.
FIG. 1 shows the layout of part of a cell array of a conventional NOR flash memory device, and FIG. 2 is a section view of a unit cell of the NOR flash memory device, taken along line II--II of FIG. 2.
In the conventional NOR flash memory device of FIG. 1, a unit cell is formed in a region where a bit line (B/L) crosses a word line (W/L) at a right angle. The unit cell has a floating gate 7 and a control gate 11 stacked therein. Two unit cells are connected to a bit line (B/L) via a bit line contact region 13. Also, an active source region 15 parallel with the word line (W/L) is connected to a source line (S/L) parallel with the bit line, via a common source contact region 17. The active source region 15 is an impurity region formed by implanting impurities into a substrate 1. Also, as shown in FIG. 2, the unit cell of the conventional NOR flash memory device includes the floating gate 7, a dielectric layer 9 formed on the floating gate 7, and the control gate 11 formed on the dielectric layer 9. A tunnel oxide layer 5 is interposed between the floating gate 7 and a semiconductor substrate having a source region 3a and a drain region 3b.
In the above conventional NOR flash memory device, the active source region 15 is connected to the source line (S/L) at intervals of 16 or 32 bits, via the common source contact region 17. Accordingly, if the cell area is reduced and thus an active width "t" (see FIG. 1) of the active source region 15 is reduced, resistance of the active source region 15 increases. Thus, it is impossible to quickly discharge the current of several hundred microamperes (.mu.A) generated during the operation of the cell.
Also, if all contact regions-the bit line contact region, the source contact region, and the word line contact region of a cell array region, and the active contact region and the gate contact region of a periphery region-are formed by a single photolithography process step, and etching is performed based on the bit line contact region or the source contact region of the cell array region, the active contact region and the gate contact region of the periphery region can be over-etched. Over-etching occurs because the step difference in the cell array region is larger than the step difference in the periphery region.